1. Field of the Invention
The present invention relates to a memory cell of a DRAM (Dynamic Random Access Memory) and, more particularly, to a memory cell having a structure in which a capacitor and a transistor connected thereto are stacked on a semiconductor substrate.
2. Description of the Background Art
A DRAM comprises a memory cell array serving as a storage area for storing a large amount of information, and a peripheral circuit part for causing the memory cell array to perform a predetermined input/output operation. The memory cell array has a plurality of memory cells arranged in an array and each corresponding to a minimum storage unit. A memory cell basically comprises a capacitor and a MOS (Metal Oxide Semiconductor) transistor (cell transistor) connected to the capacitor. Data values "0" and "1" (or vice versa) are associated with whether or not the capacitor stores a predetermined electric charge, and are provided for processing of the stored information.
FIG. 50 is a circuit diagram of an equivalent circuit of a typical DRAM memory cell 200A. The memory cell 200A comprises a capacitor 201 and a cell transistor 202. The capacitor 201 has a first end receiving a fixed potential, e.g. a ground potential, and a second end connected to a bit line 203 through the cell transistor 202. The cell transistor 202 has a gate electrode connected to a word line 204. A sense amplifier 205 connected to the bit line 203 is also shown in FIG. 50. The cell transistor 202 further has a pair of electrodes for establishing a connection between the bit line 203 and the capacitor 201. The pair of electrodes of the cell transistor 202 function as a source of carriers or function to drain carriers out of the cell transistor 202, and therefore are referred to hereinafter as source/drain.
In the memory cell 200A, a leakage current flows between a semiconductor substrate in which the transistor 202 is formed and the capacitor 201. The leakage current varies the electric charge on the capacitor 201 to give rise to an error of the information stored in the capacitor 201. To compensate for such variations in electric charge, the DRAM memory cells perform a refresh operation.
In the refresh operation, the sense amplifier 205 reads information from the capacitor 201, and a write operation is conducted. If it is judged that the capacitor 201 is charged, the sense amplifier 205 replenishes the capacitor 201 with a new electric charge. If it is judged that the capacitor 201 is not charged, the sense amplifier 205 eliminates the electric charge on the capacitor 201.
However, the refresh operation increases the power consumption of a chip with the increase in the number of memory cells. Furthermore, a large leakage current from the capacitor requires the refresh operation to be performed frequently. For example, conventional DRAMs must perform the refresh operation upon the information stored in all memory cells in a relatively short cycle of the order of one millisecond to hundreds of milliseconds.
While the refresh operation is being performed, the memory cells cannot read out the information stored therein. In view of this fact, the frequent refresh operation decreases the efficiency with which the information stored in the memory is used relative to the operating time.